Solid-state image sensors have found widespread use in camera systems. The solid-state image sensors in some camera systems have a matrix of photosensitive elements in series with switching and amplifying elements. The photosensitive elements may be, for example, photoreceptors, photodiodes, PIN diodes, phototransistors, charge-coupled device (CCD) gate, or other similar elements. Each photosensitive element receives incident light corresponding to a portion of a scene being imaged. A photosensitive element, along with its accompanying electronics, is called a picture element (“pixel”) or a pixel circuit. Each photosensitive element produces an electrical signal relative to the light intensity of the image. The electrical signal generated by the photosensitive element is typically a current proportional to the amount of electromagnetic radiation (light) incident on the photosensitive element.
Many image sensors are implemented using metal oxide semiconductor (MOS) or complimentary metal oxide semiconductor (CMOS) technology. Image sensors with passive pixels and image sensors with active pixels are distinguished within the MOS and CMOS imaging technologies. An active pixel amplifies/buffers the charge that is collected on its photosensitive element. A passive pixel does not perform signal amplification and employs a charge sensitive amplifier that is not integrated in the pixel.
FIG. 1 illustrates a conventional active pixel circuit. The illustrated pixel circuit behaves as a source follower during both pixel reset and pixel readout. A photodiode, DP, produces a photo current, IP, proportional to the incident light intensity. The photo current is integrated on a sense capacitor, CS. The sense capacitor is typically a parasitic reverse-biased PN junction capacitance associated with the photodiode and other parasitic capacitance. A sense MOS transistor, M2, operates as a source follower that buffers the voltage on the sense node, Node 1, nondestructively to a column line, COL. A row select MOS transistor, M3, acting as a switch, activates the source follower transistor when the particular row including the pixel is selected. When the pixel is reset, the gate of a reset MOS transistor, M1, is brought up to a driving voltage, VDD, for example, and the voltage on the sense capacitor is reset to approximately VDD-VTH, where VTH is the threshold voltage of the reset transistor.
The reset level contains an error from pixel to pixel. The error has two components: a fixed error component and a random reset noise. The fixed error results from mismatches between the threshold voltage and transistor sizes. The fixed error is also referred to as fixed pattern noise (FPN). FPN negatively affects the uniformity of the pixel responses in the pixel array. Correction of this non-uniformity may require some type of calibration, for example, by multiplying or adding/subtracting the pixel's signal with a correction amount that is pixel dependent. Conventional technologies to cancel FPN may be referred to as correlated double sampling, uncorrelated double sampling, or offset compensation, and are discussed in more detail below.
The random reset noise (also referred to as reset noise) is generated during the reset process for the pixel. The shot noise in the reset transistor during reset is band-limited by the transconductance of the reset transistor and the sense capacitor. This produces a root-mean-square (RMS) noise at the sense node. This RMS noise is described by the following equation:
            kT              2        ⁢                  C          S                      ,  where CS is the capacitance of the sense capacitor, T is the absolute temperature (Kelvin) of the reset transistor, and k is Boltzman's constant. This RMS noise may be sampled on the sense capacitor when the reset process is complete. As an example, the sampled RMS noise is 643 μV for a typical sense capacitor value of 5 fF at room temperature.
In principle, both the fixed and random error components can be removed by correlated double sampling (CDS). Two voltage measurements are used to perform CDS. A first voltage (the reset value) is the pixel voltage immediately following the reset. This measurement includes both the fixed and random components of the reset level error. The reset value may be stored in either analog or digital form. The second voltage (the integration value) is the pixel voltage after the integration period. The integration value contains the same error components introduced upon reset because the pixel has not been reset again. Additionally, the integration value includes the change in voltage due to the integrated photo current. A CDS circuit (not shown) outside the pixel circuit subtracts the reset value from the integrated value, leaving only the light response term—the photo response voltage, VP. Thus, a CDS circuit removes both the FPN and the random reset noise. The photo response voltage, which is the difference between the integrated value and the reset value, is described by the following equation:
            V      P        =                            I          P                ⁢                  T          INT                            C        S              ,where IP is the integrated current on the sense capacitor, TINT is the integration period during which the photo current is integrated on the sense capacitor, and CS is the capacitance of the sense capacitor.
One drawback of conventional CDS technology is that the reset value is stored for the duration of the integration period, which can approach the frame period. A storage circuit (not shown) holds the value for this entire period. For a typical imager that operates at 30 frames per second, the storage period is 33 ms. Analog sample-and-hold circuits use large and expensive hold capacitors to achieve such a long hold time. Moreover, the storage circuit stores the reset values for the entire array of pixels because each pixel value is used for the resulting image. Although a frame buffer could be used to store the reset values for all the pixels, analog and digital frame buffers are impractical. Analog frame buffers consume significant chip area and draw substantial electrical power. For this reason, most frame buffers are digital. Digital frame buffers, however, also consume significant chip area and are expensive.
An alternative approach of providing CDS without frame buffers is to use a pinned diode as the photodiode. A pinned diode pixel works much the same way as a CCD pixel. However, the pixels based on pinned diodes require additional semiconductor processing steps and also reduce the fill factor of the pixel.
To circumvent the problems associated with CDS technology, many CMOS imagers employ uncorrelated double sampling (UDS) (although many publications use the term CDS to generically describe both CDS and UDS). A UDS circuit (not shown) uses the pixel voltage of the reset period subsequent to the current integration period, rather than the reset period prior to the integration period. In other words, a UDS circuit subtracts the subsequent reset value from the current integration value. Since the reset for a subsequent frame occurs immediately after the integration measurement of the current frame, the timeframe for storing the integration and reset values is relatively short. Typically, these measurements are held in capacitors in a switched-capacitor subtractor.
Although UDS technology removes the fixed error (FPN) due to the threshold voltage and transistor size mismatches, it does not reduce the random reset noise because the reset noise introduced during the subsequent reset (i.e., for the next frame) is not correlated with the reset noise of the current frame. As a result, UDS technology actually increases total RMS reset noise by a factor of the square root of two because two uncorrelated noise quantities are present after the subtraction. Therefore, UDS is also unsatisfactory to reduce the reset noise.
One attempt to address the unresolved problem of random reset noise is discussed in U.S. Pat. No. 6,697,111 to Kozlowski et al. The U.S. Pat. No. 6,697,111 is directed to a three transistor CMOS pixel circuit coupled to a tapered reset supply that supplies a tapered reset waveform to the pixel circuit to reduce the reset noise. FIG. 2 illustrates the conventional pixel circuit, including a reset (RST) MOS field effect transistor (MOSFET), a row select MOSFET, and a dual-driver MOSFET. The illustrated pixel circuit behaves as a distributed transimpedance amplifier during pixel reset and as a source follower driver during pixel readout.
FIG. 3 illustrates a conventional tapered reset clocking waveform. The illustrated waveform includes a reset voltage of about 3.0 volts that is supplied for a reset period. Then the waveform is gradually and continuously tapered to a subthreshold voltage of approximately 2.0 volts. The application of the tapered reset waveform to the transimpedance amplifier of the pixel circuit enables the reset noise envelope to decay before the reset switch (i.e., the reset MOSFET) is completely opened.
As noted in U.S. Pat. No. 6,697,111, the timing of the tapered waveform can affect the performance of the pixel circuit and imager. Specifically, decreasing the voltage too quickly reduces the noise suppression benefits of the tapered waveform. On the other hand, decreasing the voltage too slowly may interfere with faster imaging rates such as those used for video imaging. Therefore, the duration of the tapered portion of the waveform may have many potentially negative affects on the performance of the imager. Of course, the gradual slope of the continuously tapered waveform determines, at least in part, the time between the reset and extinguishing the reset noise, and vice versa.